Clifford

• @oe1cxw

Presentations:

• 2016-12-28 17:15 - 33C3 (2016) - Formal Verification of Verilog HDL with Yosys-SMTBMC
• 2015-12-27 16:00 - 32C3 (2015) - A Free and Open Source Verilog-to-Bitstream Flow for iCE40 FPGAs