A Free and Open Source Verilog-to-Bitstream Flow for iCE40 FPGAs

Presented at 32C3 (2015), Dec. 27, 2015, 4 p.m. (60 minutes).

Yosys (Yosys Open Synthesis Suite) is an Open Source Verilog synthesis and verification tool. Project IceStorm aims at reverse engineering and documenting the bit-stream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bit-stream files, including a tool that converts iCE40 bit-stream files into behavioral Verilog. Currently the bitstream format for iCE40 HX1K and HX8K is fully documented and supported by the tools. Arachne-PNR is an Open Source place&route tool for iCE40 FPGAs based on the databases provided by Project IceStorm. It converts BLIF files into an ASCII file format that can be turned into a bit-stream by IceStorm tools. This three projects together implement a complete open source tool-chain for iCE40 FPGAs. It is available now and it is feature complete (with the exception of timing analysis, which is work in progress).

Presenters:

• Clifford

Links:

• https://fahrplan.events.ccc.de/congress/2015/Fahrplan/events/7139.html

Similar Presentations:

• 33C3 (2016) / Fnord-Jahresrückblick: Stream
• 33C3 (2016) / Formal Verification of Verilog HDL with Yosys-SMTBMC
• DEF CON 18 (2010) / FPGA Bitstream Reverse Engineering